Analog-to-digital converters (ADCs) are used in a wide range of applications. The operational requirements of an ADC depend on the application, and typically include a minimum speed of response and a minimum resolution. Furthermore, the power consumption of the device can for some applications be important.
Two commonly used types of ADC are the successive approximation register (SAR) ADC, and the sigma delta (ΣΔ) ADC. A typical SAR ADC comprises a comparator 101 and a shift register and SAR logic 103, which is clocked by means of clock generator 102, as shown in FIG. 1. The shift register provides the ADC results. In operation, the voltage input vi is compared with reference voltages vc: if the input voltage is higher than the reference level or reference voltage (which is set to one half of an initial reference voltage Vref), a logical “1” is shifted into the shift register; conversely, if the input voltage is less than the reference level, a logical “0” is shifted into the shift register. Next, the reference level vc is either increased or decreased by one quarter the original reference voltage, depending on the whether the comparison output produced a “1” or a “0”. In the next iteration, the input voltage is compared with the reference level (which is now either three-quarters or one quarter of the initial reference voltage), and again a “1” or a “0” shifted into the shift register in dependence on the comparison result. In successive stages, the reference level is shifted up or down by a successively smaller amounts (⅛ the initial voltage, 1/16 the initial voltage and so on), a further bit being added to the shift register at each stage. In order to increase the resolution of the SAR ADC, a single further iteration is required
A typical sigma delta ADC, also hereinafter referred to as a delta-sigma ADC, is based on sigma-delta modulation (SDM), as illustrated in FIG. 2. FIG. 2 shows a conventional sigma-delta modulator comprising a loop filter 201, a quantizer 202 and a feedback path including a digital-to-analog converter DAC 203, which performs digital to analog conversion based on a reference signal Vref. The output of the DAC 203 is subtracted from the input signal at a summing node 204. Sigma-delta modulators act as a low-pass filter to the input signal and a high pass filter to quantization noise. The output of the quantizer is further processed in a digital decimation filter. A sigma-delta ADC therefore consists of the combination of a sigma-delta modulator and a decimation filter.
In a first order sigma-delta converter, in order to add a single bit to the resolution, it is necessary to double the number of steps or iterations.
Higher order SDMs, with more integrators in the forward path, are known, in which the resolution increases more than linearly—although not as rapidly as a in a typical SAR; however these are generally more complex, and may have lower stability. The skilled person will appreciate that, with regard to resolution, the effective number of bits (ENOB) is related to the number of conversion steps N as follows:                1st order: ENOB=log2(N),        2nd order: ENOB<2*log2(N)Or in other words, for the same number of cycles, a 2nd order modulator has almost twice the resolution (in bits) as a 1st order modulator, albeit with higher complexity (and typically higher power requirements).        
United States patent application publication number US 2008/0258 951, also published as U.S. Pat. No. 7,504,977, discloses a hybrid delta-sigma/SAR analog-to-digital converter and methods for using such, wherein a delta sigma ADC is used to provide a first portion of the conversion result, and finer resolution—that is to say, a second portion of the result—is provided by an SAR ADC. Since the conversion time required to provide successively finer resolution using a delta-sigma ADC increases exponentially with the number of bits, the sigma delta ADC is used only for the most significant bits, and an SAR is used for the remaining, or less significant, bits, which speeds up the operation. However, the accuracy of this hybrid ADC is limited by the matching of the capacitors (or other elements) used to define the comparison levels of the successive approximation step.
A low-power digital temperature sensor comprising a sigma delta ADC converter is disclosed in the datasheet TMP102 of Texas Instruments.
There remains an ongoing need for a low-power, accurate ADC, and for such an ADC which is compatible with temperature sensing in non-contact transponders.